PMC.HASWELLUC(3) FreeBSD Library Functions Manual PMC.HASWELLUC(3)
NAME
pmc.haswelluc - uncore measurement events for Intel Haswell family CPUs
LIBRARY
Performance Counters Library (libpmc, -lpmc)
SYNOPSIS
#include <pmc.h>
DESCRIPTION
Intel Haswell CPUs contain PMCs conforming to version 3 of the Intel
performance measurement architecture. These CPUs contain two classes of
PMCs:
PMC_CLASS_UCF Fixed-function counters that count only one hardware
event per counter.
PMC_CLASS_UCP Programmable counters that may be configured to count
one of a defined set of hardware events.
The number of PMCs available in each class and their widths need to be
determined at run time by calling pmc_cpuinfo(3).
Intel Haswell PMCs are documented in Combined Volumes: 1, 2A, 2B, 2C, 3A,
3B and 3C, Intel(R) 64 and IA-32 Architectures Software Developers
Manual, Order Number: 325462-045US, Intel Corporation, January 2013.
HASWELL UNCORE FIXED FUNCTION PMCS
These PMCs and their supported events are documented in pmc.ucf(3). Not
all CPUs in this family implement fixed-function counters.
HASWELL UNCORE PROGRAMMABLE PMCS
The programmable PMCs support the following capabilities:
Capability Support
PMC_CAP_CASCADE No
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT No
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE No
PMC_CAP_SYSTEM No
PMC_CAP_TAGGING No
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER No
PMC_CAP_WRITE Yes
Event Qualifiers
Event specifiers for these PMCs support the following common qualifiers:
cmask=value
Configure the PMC to increment only if the number of configured
events measured in a cycle is greater than or equal to value.
edge Configure the PMC to count the number of de-asserted to asserted
transitions of the conditions expressed by the other qualifiers.
If specified, the counter will increment only once whenever a
condition becomes true, irrespective of the number of clocks
during which the condition remains true.
inv Invert the sense of comparison when the "cmask" qualifier is
present, making the counter increment when the number of events
per cycle is less than the value specified by the "cmask"
qualifier.
Event Specifiers (Programmable PMCs)
Haswell programmable PMCs support the following events:
UNC_CBO_XSNP_RESPONSE.MISS
(Event 22H, Umask 01H) A snoop misses in some processor core.
UNC_CBO_XSNP_RESPONSE.INVAL
(Event 22H, Umask 02H) A snoop invalidates a non-modified line in
some processor core.
UNC_CBO_XSNP_RESPONSE.HIT
(Event 22H, Umask 04H) A snoop hits a non-modified line in some
processor core.
UNC_CBO_XSNP_RESPONSE.HITM
(Event 22H, Umask 08H) A snoop hits a modified line in some
processor core.
UNC_CBO_XSNP_RESPONSE.INVAL_M
(Event 22H, Umask 10H) A snoop invalidates a modified line in
some processor core.
UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER
(Event 22H, Umask 20H) Filter on cross-core snoops initiated by
this Cbox due to external snoop request.
UNC_CBO_XSNP_RESPONSE.XCORE_FILTER
(Event 22H, Umask 40H) Filter on cross-core snoops initiated by
this Cbox due to processor core memory request.
UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER
(Event 22H, Umask 80H) Filter on cross-core snoops initiated by
this Cbox due to LLC eviction.
UNC_CBO_CACHE_LOOKUP.M
(Event 34H, Umask 01H) LLC lookup request that access cache and
found line in M-state.
UNC_CBO_CACHE_LOOKUP.ES
(Event 34H, Umask 06H) LLC lookup request that access cache and
found line in E or S state.
UNC_CBO_CACHE_LOOKUP.I
(Event 34H, Umask 08H) LLC lookup request that access cache and
found line in I-state.
UNC_CBO_CACHE_LOOKUP.READ_FILTER
(Event 34H, Umask 10H) Filter on processor core initiated
cacheable read requests. Must combine with at least one of 01H,
02H, 04H, 08H.
UNC_CBO_CACHE_LOOKUP.WRITE_FILTER
(Event 34H, Umask 20H) Filter on processor core initiated
cacheable write requests. Must combine with at least one of 01H,
02H, 04H, 08H.
UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER
(Event 34H, Umask 40H) Filter on external snoop requests. Must
combine with at least one of 01H, 02H, 04H, 08H.
UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER
(Event 34H, Umask 80H) Filter on any IRQ or IPQ initiated
requests including uncacheable, non-coherent requests. Must
combine with at least one of 01H, 02H, 04H, 08H.
UNC_ARB_TRK_OCCUPANCY.ALL
(Event 80H, Umask 01H) Counts cycles weighted by the number of
requests waiting for data returning from the memory controller.
Accounts for coherent and non-coherent requests initiated by IA
cores, processor graphic units, or LLC.
UNC_ARB_TRK_REQUEST.ALL
(Event 81H, Umask 01H) Counts the number of coherent and in-
coherent requests initiated by IA cores, processor graphic units,
or LLC.
UNC_ARB_TRK_REQUEST.WRITES
(Event 81H, Umask 20H) Counts the number of allocated write
entries, include full, partial, and LLC evictions.
UNC_ARB_TRK_REQUEST.EVICTIONS
(Event 81H, Umask 80H) Counts the number of LLC evictions
allocated.
UNC_ARB_COH, Umask TRK_OCCUPANCY.ALL
(Event 83H, Umask 01H) Cycles weighted by number of requests
pending in Coherency Tracker.
UNC_ARB_COH, Umask TRK_REQUEST.ALL
(Event 84H, Umask 01H) Number of requests allocated in Coherency
Tracker.
SEE ALSO
pmc(3), pmc.atom(3), pmc.core(3), pmc.corei7(3), pmc.corei7uc(3),
pmc.haswell(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.sandybridge(3),
pmc.sandybridgeuc(3), pmc.sandybridgexeon(3), pmc.soft(3), pmc.tsc(3),
pmc.ucf(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3),
pmclog(3), hwpmc(4)
HISTORY
The pmc library first appeared in FreeBSD 6.0.
AUTHORS
The Performance Counters Library (libpmc, -lpmc) library was written by
Joseph Koshy <jkoshy@FreeBSD.org>. The support for the Haswell
microarchitecture was added by Hiren Panchasara
<hiren.panchasara@gmail.com>.
FreeBSD 13.1-RELEASE-p6 March 22, 2013 FreeBSD 13.1-RELEASE-p6
man2web Home...