PMC.K7(3)              FreeBSD Library Functions Manual              PMC.K7(3)

NAME
     pmc.k7 - measurement events for AMD Athlon (K7 family) CPUs

LIBRARY
     Performance Counters Library (libpmc, -lpmc)

SYNOPSIS
     #include <pmc.h>

DESCRIPTION
     AMD K7 PMCs are present in the AMD Athlon series of CPUs and are
     documented in: AMD Athlon Processor x86 Code Optimization Guide,
     Publication No. 22007, Advanced Micro Devices, Inc., February 2002.

   PMC Features
     AMD K7 PMCs are 48 bits wide.  Each K7 CPU contains 4 PMCs with the
     following capabilities:

     Capability           Support
     PMC_CAP_CASCADE      No
     PMC_CAP_EDGE         Yes
     PMC_CAP_INTERRUPT    Yes
     PMC_CAP_INVERT       Yes
     PMC_CAP_READ         Yes
     PMC_CAP_PRECISE      No
     PMC_CAP_SYSTEM       Yes
     PMC_CAP_TAGGING      No
     PMC_CAP_THRESHOLD    Yes
     PMC_CAP_USER         Yes
     PMC_CAP_WRITE        Yes

   Event Qualifiers
     Event specifiers for AMD K7 PMCs can have the following optional
     qualifiers:

     count=value
             Configure the counter to increment only if the number of
             configured events measured in a cycle is greater than or equal to
             value.

     edge    Configure the counter to only count negated-to-asserted
             transitions of the conditions expressed by the other qualifiers.
             In other words, the counter will increment only once whenever a
             given condition becomes true, irrespective of the number of
             clocks during which the condition remains true.

     inv     Invert the sense of comparison when the "count" qualifier is
             present, making the counter to increment when the number of
             events per cycle is less than the value specified by the "count"
             qualifier.

     os      Configure the PMC to count events happening at privilege level 0.

     unitmask=mask
             This qualifier is used to further qualify a select few events,
             "k7-dc-refills-from-l2", "k7-dc-refills-from-system" and
             "k7-dc-writebacks".  Here mask is a string of the following
             characters optionally separated by `+' characters:

             m       Count operations for lines in the "Modified" state.
             o       Count operations for lines in the "Owner" state.
             e       Count operations for lines in the "Exclusive" state.
             s       Count operations for lines in the "Shared" state.
             i       Count operations for lines in the "Invalid" state.

             If no "unitmask" qualifier is specified, the default is to count
             events for caches lines in any of the above states.

     usr     Configure the PMC to count events occurring at privilege levels
             1, 2 or 3.

     If neither of the "os" or "usr" qualifiers were specified, the default is
     to enable both.

   AMD K7 Event Specifiers
     The event specifiers supported on AMD K7 PMCs are:

     k7-dc-accesses
             (Event 40H) Count data cache accesses.

     k7-dc-misses
             (Event 41H) Count data cache misses.

     k7-dc-refills-from-l2 [,unitmask=mask]
             (Event 42H) Count data cache refills from L2 cache.  This event
             may be further qualified using the "unitmask" qualifier.

     k7-dc-refills-from-system [,unitmask=mask]
             (Event 43H) Count data cache refills from system memory.  This
             event may be further qualified using the "unitmask" qualifier.

     k7-dc-writebacks [,unitmask=mask]
             (Event 44H) Count data cache writebacks.  This event may be
             further qualified using the "unitmask" qualifier.

     k7-hardware-interrupts
             (Event CFH) Count the number of taken hardware interrupts.

     k7-ic-fetches
             (Event 80H) Count instruction cache fetches.

     k7-ic-misses
             (Event 81H) Count instruction cache misses.

     k7-interrupts-masked-cycles
             (Event CDH) Count the number of cycles when the processor's IF
             flag was zero.

     k7-interrupts-masked-while-pending-cycles
             (Event CEH) Count the number of cycles interrupts were masked
             while pending due to the processor's IF flag being zero.

     k7-l1-and-l2-dtlb-misses
             (Event 46H) Count L1 and L2 DTLB misses.

     k7-l1-dtlb-miss-and-l2-dtlb-hits
             (Event 45H) Count L1 DTLB misses and L2 DTLB hits.

     k7-l1-itlb-misses
             (Event 84H) Count L1 ITLB misses that are L2 ITLB hits.

     k7-l1-l2-itlb-misses
             (Event 85H) Count L1 (and L2) ITLB misses.

     k7-misaligned-references
             (Event 47H) Count misaligned data references.

     k7-retired-branches
             (Event C2H) Count all retired branches (conditional,
             unconditional, exceptions and interrupts).

     k7-retired-branches-mispredicted
             (Event C3H) Count all mispredicted retired branches.

     k7-retired-far-control-transfers
             (Event C6H) Count retired far control transfers.

     k7-retired-instructions
             (Event C0H) Count all retired instructions.

     k7-retired-ops
             (Event C1H) Count retired ops.

     k7-retired-resync-branches
             (Event C7H) Count retired resync branches (non control transfer
             branches).

     k7-retired-taken-branches
             (Event C4H) Count retired taken branches.

     k7-retired-taken-branches-mispredicted
             (Event C5H) Count mispredicted taken branches that were retired.

   Event Name Aliases
     The following table shows the mapping between the PMC-independent aliases
     supported by Performance Counters Library (libpmc, -lpmc) and the
     underlying hardware events used.

     Alias                 Event
     branches              k7-retired-branches
     branch-mispredicts    k7-retired-branches-mispredicted
     dc-misses             k7-dc-misses
     ic-misses             k7-ic-misses
     instructions          k7-retired-instructions
     interrupts            k7-hardware-interrupts
     unhalted-cycles       (unsupported)

SEE ALSO
     pmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.k8(3),
     pmc.soft(3), pmc.tsc(3), pmclog(3), hwpmc(4)

HISTORY
     The pmc library first appeared in FreeBSD 6.0.

AUTHORS
     The Performance Counters Library (libpmc, -lpmc) library was written by
     Joseph Koshy <jkoshy@FreeBSD.org>.

FreeBSD 13.1-RELEASE-p6         October 4, 2008        FreeBSD 13.1-RELEASE-p6